This invention relates to a system for accessing memory and more particularly to intelligently interleaving accesses to a multibank memory.
Network processing devices, such as routers, switches, concentrators, gateways, etc., receive packets from multiple input ports. It is desirable to route these packets as quickly as possible to the correct destination address through corresponding output ports. Headers in the incoming packets are read to determine the correct output ports for the incoming packets. The incoming packets are temporarily stored in a memory buffer until the output ports assigned to the incoming packets are scheduled to forward the packets to the appropriate destination address.
The memory buffer must be large to handle the large number of packets received at the input ports and to temporarily store large bursts of packets that could be received on one or more of the input ports. Certain memory devices, such as Dynamic Random Access Memories (DRAMs), are more cost effective than Static Random Access Memory (SRAM) in large memory applications. However, several clock cycles are required for precharging the memory banks each time the DRAM is accessed. This DRAM activation time overhead does not pose a significant time cost when large packets are stored in memory. However, when small packets are stored in the DRAM, the access required to read or write each packet presents a substantial bottleneck in the overall rate that packets can be processed by the network processing device.
The present invention addresses this and other problems associated with the prior art.
A network processing device intelligently interleaves packets for read and write access requests in a multibank memory. The system intelligently writes packets into the different memory banks so that the same memory bank is not used for back-to-back packet reads. The last memory bank write is determined for each output queue in the network processing device. This last bank information is used in combination with look ahead packet read information for a group of packets from the next output queue scheduled to read packets from memory. The scheduler uses all this information to avoid any back-to-back packet read, write, or read/write accesses to the same memory bank. This intelligent packet interleaving scheme preserves memory bus bandwidth that would normally be wasted accessing the same memory banks.